Truncation noise in fixed-point SFGs

Introduction: Traditionally, much of the research into estimating the effects of truncation and roundoff noise in fixed-point systems has been focused on the implementation within, or design of, a digital signal processing (DSP) processor. This leads to certain constraints on and assumptions about quantisation errors: for example that the wordlength at all signals in the signal flow graph (SFG) is constant, and that the wordlength before a quantisation is much greater than after (for example after a multiply). When designing custom hardware to implement DSP functions, we may often be freed from these constraints. In this context, we report in this Letter some alternative truncation-noise models that have been developed as part of a high-level synthesis system for the mapping of an SFG to hardware implementation in a field programmable gate array (FPGA). To reduce as much as possible the wastage of FPGA resources, we are specifically interested in the truncation rather than rounding of results. The effects of finite register length in fixed-point systems have been studied for some time. Oppenheim and Weinstein [1] and Liu [2] presented standard models for quantisation errors and error propagation through linear time-invariant systems, based on linearising the truncation of signals. Error signals, assumed to be uniformly distributed, white and uncorrelated, are added whenever a truncation occurs. This approximate model has served very well, since the quantisation error power is dramatically affected by the signal width in a uniform-width structure, meaning that it is only necessary to have models accurate to within 30– 40% in order to predict the required signal width [3]. However, in a system realisation where different signals may have different wordlengths, it is possible to improve on these models.